The semiconductor integrated circuit (IC) industry has experienced rapid growth. Continuing advances in semiconductor manufacturing processes have resulted in semiconductor devices with finer features and/or higher degrees of integration. Functional density (i.e., the number of interconnected devices per chip area) has generally increased while feature size (i.e., the smallest component that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs.
A chip package not only provides protection for semiconductor devices from environmental contaminants, but also provides a connection interface for the semiconductor devices packaged therein. Packaging technologies can be divided into multiple categories. In one of the categories of packaging, dies are sawed from wafers before they are packaged onto other wafers, and “known-good-dies” are packaged. An advantage of this packaging technology is the possibility of forming fan-out chip packages, which means that I/O pads on a die can be redistributed to a greater area than the die itself. Therefore, the number of I/O pads packed on the surfaces of the dies can be increased.
New packaging technologies have been developed to further improve the density and functions of semiconductor dies. These relatively new types of packaging technologies for semiconductor dies face manufacturing challenges, and they have not been entirely satisfactory in all respects.